1. Field of the Invention
The present invention is generally related to I/O bus structures. More particularly, the present invention is related to configuring in real time an ASIC I/O bus structure to communicate with multiple external devices having different bus structures.
2. Background Art
Current ASIC architectures have “hardwired” I/O bus structures. In a multi-I/O bus system, the drawbacks of a hardwired I/O bus structure may include requiring: (1) more ASIC package pins; (2) external glue logic; or (3) an external bus bridge IC.
FIG. 1A is a diagram illustrating an application-specific integrated circuit (ASIC) having multi-I/O bus structures communicating with two devices having different I/O bus structures. FIG. 1A shows ASIC 102, device 104, device 106, and device 108. ASIC 102 contains two bus structures, a local bus structure 110 (e.g., Expansion Bus Interface, or EBI) for communicating with device 104 and a PCI bus structure 112 for communicating with devices 106 and 108. Thus, ASIC 102 contains pins for a local bus 110 and pins for a PCI bus 112.
FIG. 1B shows additional detail of the ASIC 102. As shown in FIG. 1B, the ASIC 102 includes an internal bus 120, a CPU interface 126, other internal resources 128, 130, and two interfaces to external buses, e.g., an EBI bus interface 122 and a PCI bus interface 124, which connect to the EBI bus 110 and the PCI bus 112, respectively.
To support the different interfaces, i.e., EBI bus 110 and PCI bus 112, ASIC 102 is required to have more pins on the package. The more pins required for the ASIC 102, the more costly the ASIC will be to manufacture.
Accordingly, what is needed is a system and method for redefining an ASIC's I/O bus structure in real-time to enable operation in a multi-PO bus system.